Re: FPGA implementation of PSK31 (learning verilog)

Kristoff Bonne

Hi Steve,

On "what language to use" issue, I actually started out with VHDL. Sofar
I wrote (or "designed") some small things in VHDL (a UART and a
SPI-interface) but as there is also a lot of code available in verilog
I guess it is interesting to have at least some basic knowledge of
verilog too.

For the PSK31, my idea was to start out with a basic DDS design and work
from there.

The main difference I see between just creating a sinewave with a DDS
and PSK31 is that the latter not just changes the phase of the signal,
but also its amplitute.
The carrier-signal seams to be "squelched" during every bittransition
(i.e. when transmitting a "0", when the phase of the signal gets inverted). I guess the best way to do this is to mulitply the sinewave
with some kind of "slope" function.

I have here C-code that implements a DDS on a attiny, so I'll use the
underlying ideas to try to implement this on a FPGA, but a MCU does not
have sufficent CPU-power for the multiplications needed during the
change when signal is inverted.
I guess a FPGA should be able to do this without to much effort.

kristoff - ON1ARF

On 29-12-16 15:13, N2CKH [digitalradio] wrote:

Hi Kristoff,

VHDL is good as its based on Ada, which is very popular in Europe as a
GP language. A Pascal implementation of PSK31 would be a good thing
for you to review. Many years ago now I was an Applications Sales
Engineer for FPGA/ASIC EDA tools such as Modelsim and prior to that
performed Ada development. However it has been a long time now that I
live in C and C++. I am currently focused on use of a TI/BIOS DSP
development board using C for my interests.

/s/ Steve, N2CKH

At 08:46 AM 12/29/2016, you wrote:
Hi all,

A couple of months ago, I started playing around with FPGAs (VHDL) to
learn more about this.

A nice next exercise might to be try to build a PSK31 modulator using
standard Direct Synthesis plus a R/2R resistor ladder. This looks to be
quite straight-forward DDS so should not be to difficult as an exercise,
but it should also be nice experiment to see what frequency you can get
out of a DDS implemented on a cheap 50 Mhz FPGA-board.

Does anybody have any experience with this?
No, I'm not asking for source-code, just to know if somebody has any
"do"'s or "don't"s I should be aware of?

I checked on github but did not find anything.

kristoff - ON1ARF

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