Re: FPGA implementation of PSK31 (learning verilog)
Hi Steve,toggle quoted messageShow quoted text
On "what language to use" issue, I actually started out with VHDL. Sofar
I wrote (or "designed") some small things in VHDL (a UART and a
SPI-interface) but as there is also a lot of code available in verilog
I guess it is interesting to have at least some basic knowledge of
For the PSK31, my idea was to start out with a basic DDS design and work
The main difference I see between just creating a sinewave with a DDS
and PSK31 is that the latter not just changes the phase of the signal,
but also its amplitute.
The carrier-signal seams to be "squelched" during every bittransition
(i.e. when transmitting a "0", when the phase of the signal gets inverted). I guess the best way to do this is to mulitply the sinewave
with some kind of "slope" function.
I have here C-code that implements a DDS on a attiny, so I'll use the
underlying ideas to try to implement this on a FPGA, but a MCU does not
have sufficent CPU-power for the multiplications needed during the
change when signal is inverted.
I guess a FPGA should be able to do this without to much effort.
kristoff - ON1ARF
On 29-12-16 15:13, N2CKH email@example.com [digitalradio] wrote: