FPGA implementation of PSK31 (learning verilog)

Kristoff Bonne

Hi all,

A couple of months ago, I started playing around with FPGAs (VHDL) to learn more about this.

A nice next exercise might to be try to build a PSK31 modulator using standard Direct Synthesis plus a R/2R resistor ladder. This looks to be quite straight-forward DDS so should not be to difficult as an exercise, but it should also be nice experiment to see what frequency you can get out of a DDS implemented on a cheap 50 Mhz FPGA-board.

Does anybody have any experience with this?
No, I'm not asking for source-code, just to know if somebody has any "do"'s or "don't"s I should be aware of?

I checked on github but did not find anything.

kristoff - ON1ARF

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